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Instruction set architecture
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#	Item
641	SPARC64™ XIfx: Fujitsu’s Next Generation Processor for HPC August 11, 2014 Toshio Yoshida Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-04 15:04:55 SPARC64 VI Fujitsu Instruction set architectures Parallel computing SPARC64 V SPARC64 K computer Multi-core processor SPARC Computer hardware Computer architecture Central processing unit
642	Platform-Independent Programs Sang Kil Cha, Brian Pak, David Brumley Richard J. Lipton Carnegie Mellon University Add to Reading List Source URL: users.ece.cmu.edu Language: English - Date: 2014-05-29 15:38:01 Shellcode NOP X86 Portable Executable Instruction set Assembly language Self-modifying code QEMU Branch Computer architecture Computing Instruction set architectures
643	Virtex-5 Product Presentation Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:06:41 Reconfigurable computing Xilinx PowerPC Field-programmable gate array PowerPC 400 Computer architecture Electronic engineering Instruction set architectures
644	PDF Document Add to Reading List Source URL: www.klabs.org Language: English - Date: 2009-01-15 19:31:05 Restart Exception handling Computing Embedded systems Instruction set architectures BIOS Computer architecture Apollo Guidance Computer Interrupts
645	Title (Verdana Bold 18pt) Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:17:47 X86 architecture X86 Advanced Micro Devices Computer architecture Bobcat Instruction set architectures
646	Hummingbird: A Low-Cost Superscalar PA-RISC Processor Stephen Undy Hewlett-Packard Hot Chips V Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:45:25 Computer memory Instruction set architectures Central processing unit CPU cache Cache PA-RISC Reduced instruction set computing Hewlett-Packard Dynamic random-access memory Computer hardware Computing Computer architecture
647	Microsoft Word - 18-Processor-Architectures.doc Add to Reading List Source URL: dragonbook.stanford.edu Language: English - Date: 2008-09-08 17:21:14 Central processing unit Assembly languages Instruction set architectures Classes of computers Models of computation Stack machine Addressing mode Instruction set Accumulator Computer architecture Computing Computer hardware
648	HC17.S4T1 Telairity-1 A Real Time H.264 High Definition Video Architecture.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:46:07 Computer hardware 64-bit CPU cache Instruction set Scalar processor CDC Cyber Comparison of CPU architectures Computer architecture Computing Central processing unit
649	CLOUD TRANSFORMS IT BIG DATA TRANSFORMS BUSINESS Pat Gelsinger Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:27:56 Instruction set architectures EMC Corporation Xeon Intel Core Pat Gelsinger Intel X86 Computer architecture Computing Computer hardware
650	The LIFE Family of High Performance Single Chip VLIWs Gerrit A. Siavenburg, Philips Research Palo Alto Andrew S. Huang, Carnegie Mellon University1 Yen C. Lee, Philips Research Palo Alto Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:28 Reduced instruction set computing VAX Central processing unit Very long instruction word Benchmark Computer architecture Computing Instruction set architectures

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